In the field of radio frequency (RF) transceivers, even-numbered frequency dividers are used within synthesizers to generate quadrature (I/Q) local oscillator (LO) signals. FIG. 1 illustrates an example of such a conventional synthesizer 100. The synthesizer 100 consists of one or more 1/M frequency divider circuits 110, 120. Each frequency divider circuit 110, 120 comprises M flip-flops 112, 114, 116 coupled in a loop whereby the outputs of each flip-flop 112, 114, 116 are coupled to respective inputs of the next flip-flop in the loop, with the exception of the Mth flip-flop 116 whose outputs are inversely coupled to the inputs of the first flip-flop 112 such that the non-inverted output of the Mth flip-flop 116 is coupled to the inverted input of the first flip-flop 112 whilst the inverted output of the Mth flip-flop 116 is coupled to the non-inverted input of the first flip-flop 112.
A timing signal 125 to be divided is provided to the clock inputs of each of the flip-flops 112, 114, 116. In this manner, a state transition resulting from the inverse coupling of the Mth flip-flop 116 to the first flip-flop 112 is shifted along the flip-flop loop by one flip-flop each clock cycle. As a result, each flip-flop output generates an oscillating signal having a frequency equal to 1/M the frequency of the timing signal 125, with the respective signal being phase-shifted relative to the signal of the preceding flip-flop by 180/M.
It is known to use even-numbered frequency dividers to generate quadrature LO signals, since generating the required 90° phase-shifted quadrature signals using an even-numbered frequency divider is relatively straightforward. In an even-numbered frequency divider, M is divisible by two. If M is divisible by two, then 90° phase-shifted signals may simply be obtained from, for example, the Mth flip-flop and the (Mth/2) flip-flop. For example, in a ½ frequency divider, the signal output by the first flip-flop 112 will be phase-shifted with respect to the Mth (2nd) flip-flop 116 by 180/2, i.e. by 90°. Thus, the 90° phase-shifted quadrature signals may be obtained from an output of the 2nd (Mth) flip-flop 116 and the 1st (Mth/2) flip-flop 112.
Conversely, if M is not divisible by two (e.g. M=3), a second frequency divider circuit 120 comprising flip-flops arranged to receive timing signal 125 at their clock inputs may be used to generate frequency-divided signals. For example, where M=3, the frequency-divided signals generated by the second frequency divider circuit 120 will have flip flop outputs phase-shifted by 180°/3, i.e. by −60° with respect to one another.
Thus, even-numbered frequency division lends itself to generating 90° phase-shifted signals, and thus it is relatively straightforward to generate quadrature frequency-divided signals using even-numbered frequency divider circuits.
Due to the increased number of frequency bands in cellular telecommunications standards, it is becoming increasingly desirable to be able to utilise odd-numbered division for generating local oscillator signals in order to reduce the required frequency range of the synthesizer circuits. However, unlike for even-numbered frequency division, a 90° phase-shift is not directly achievable with odd-numbered frequency division. For example, where M=3, the flip-flop generated signals will be phase-shifted with respect to one another by 180°/3, i.e. by 60°.
Thus, a need exists for an improved odd-numbered frequency divider circuit and method of operation therefor from which 90° phase-shifted quadrature signals are able to be generated.